Floating Point Coprocessors

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arranging a coprocessor
alongside a microprocessor. One technique is to provide the coprocessor with an
instruction interpreter and program counter. Each instruction fetched from
memory is examined by both the MPU and the coprocessor. If it is a MPU
instruction, the MPU executes it; otherwise the coprocessor executes it. It can
be seen that this solution is feasible, but by no means simple, as it would be
difficult to keep the MPU and coprocessor in step. Another technique is to equip
the microprocessor with a special bus to communicate with the external
coprocessor. Whenever the microprocessor encounters an operation that requires
the intervention of the coprocessor, the special bus provides a dedicated high-
speed communication between the MPU and the coprocessor. Once again, this
solution is not simple. There are more methods of connecting two (or more)
concurrently operating processors, which will be covered in more detail during
the specific discussions of the Intel and ...

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the
designers of the 68000 series of MPU's had to set aside certain bit patterns to
represent opcodes for the FPC. In the case of the 68000's, the FPC is accessed
through the opcode 1111(2). This number is the same as �F' in hexadecimal
notation, so this bit pattern is often referred to as the F-line.

Interface

The 68882 FPC employs an entirely conventional asynchronous bus
interface like all 68000 class devices, and absolutely no new signals whatsoever
are required to connect the unit to an MC 68020 MPU. The 68882 can be configured
to run under a variety of different circumstances, including various sized data
buses and clock speeds. What follows is a diagram of connections necessary ...

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